As a consequence of many factors, including demand for increased portability, computing power, memory capacity and energy efficiency in modern electronics, integrated circuits as fabricated on semiconductor substrates are continuously being reduced in size. To facilitate this size reduction, research continues into ways of reducing the sizes of integrated circuits' constituent elements. Non-limiting examples of those constituent elements include transistors, capacitors, electrical contacts, lines, and other electronic component elements. The trend of decreasing feature size is evident, for example, in memory circuits incorporated in devices such as dynamic random access memories (DRAMs), static random access memories (SRAMs), ferroelectric (FE) memories, electronically-erasable programmable read-only memories (EEPROMs), Flash memories, etc.
A NAND Flash memory chip, for example, conventionally comprises billions of identical circuit elements, known as memory cells, arranged in a plurality of arrays with associated logic circuitry. Each memory cell traditionally stores one bit of information, although multi-level cell devices can store more than one bit per cell. Each such memory cell comprises an addressable location that can store one bit (binary digit) of data. A bit can be written to a cell and read to retrieve the stored information. By decreasing the sizes of constituent elements, the conducting lines that connect them, and the conductive contacts carrying charge between them, the sizes of the elements incorporating these features can be decreased. Storage capacities and circuit speed can be increased by fitting more memory cells into a given area on the active surface of the memory device.
The continual reduction in sizes of features from which the foregoing elements are fabricated places ever-greater demands on techniques used to form the features. For example, photolithography is commonly used to pattern features on a substrate. The concept of “pitch” can be used to describe the sizing of these features. Pitch is the distance between identical points in two adjacent repetitive features. The spaces between adjacent features may be filled by another material, such as a dielectric. As a result, pitch can be viewed as the sum of the width of a feature and of the width of the space separating that feature from a neighboring feature, when that neighboring feature is part of a repeating or periodic pattern, such as may occur, for example, in an array of features.
Photoresist materials may be conventionally formulated to respond only to selected wavelengths of light. One common range of wavelengths that can be used lies in the ultraviolet (UV) range. Because many photoresist materials respond selectively to particular wavelengths, photolithography techniques each have a minimum pitch dictated by the wavelength, below which that particular photolithographic technique cannot reliably form features. Thus, the minimum pitch achievable using a particular photoresist can limit the capability for feature size reduction.
Pitch reduction techniques, often somewhat erroneously termed “pitch multiplication” as exemplified by “pitch doubling,” etc., can extend the capabilities of photolithography beyond the feature size limitations dictated by photoresists to allow creation of smaller, more densely arranged features. That is, conventional “multiplication” of pitch by a certain factor actually involves reducing the pitch by that factor. In fact, “pitch multiplication” increases the density of features by reducing pitch. Pitch thus has at least two meanings: the linear spacing between identical features in a repeating pattern; and the density or number of features per given or constant linear distance. This conventional terminology is retained herein.
Examples of such methods are described in U.S. Pat. No. 5,328,810, issued to Lowrey et al., and Patent Application Publication No. 2007/0049035, to Luan C. Tran, the entire disclosure of each of which document is incorporated herein by reference.
The critical dimension (CD) of a mask scheme or corresponding circuit element to be implemented on a given semiconductor material-based integrated circuit at a particular level is the scheme's minimum feature dimension, or the measurement of the smallest width of the smallest feature that exists in that scheme or element. Due to factors such as geometric complexity and different requirements for critical dimensions in different parts of an integrated circuit, not all features of the integrated circuit may be pitch multiplied. Furthermore, conventional pitch multiplication entails additional steps relative to conventional lithography, which can involve considerable additional time and expense. However, if some features of an integrated circuit are pitch multiplied, it is inconvenient if connecting features that interface with those features are not also pitch multiplied. Thus, superimposed features that are configured to contact each other are advantageously of similar dimensions. Such similar dimensions can enable smaller and more efficient operative components on an integrated circuit, thus increasing feature density and decreasing chip size.
Conventional methods of forming contacts through insulating materials to create electrical connections between circuit layers at different levels have not allowed the density of contacts to match the density of the features intended to be connected thereby. Accordingly, there is a need for methods of forming contacts with reduced dimensions and pitch that can match the density of the features intended to be connected by those contact features, especially where pitch multiplication is used to form the features to be connected.
Furthermore and as noted above, there is a need for a reduction in the size of integrated circuits and an increased operable density of the arrays of electrical elements on computer chips. Accordingly, a need exists for improved methods of forming features with reduced critical dimensions relative to conventional methods; improved methods for increasing feature density; methods that will produce more efficient arrays; methods that will provide more compact arrays without harming feature resolution; and methods that simplify or eliminate acts in the creation of reduced-size features.